1. Technical Field
The present invention relates to non-volatile memories and in particular to electrically erasable and programmable memories of FLASH type.
2. Description of the Related Art
The market of electrically erasable and programmable memories on silicon chips is traditionally shared between the EEPROM memory family and the FLASH memory family (or FLASH-EEPROM).
EEPROM memories comprise memory cells comprising a floating gate transistor and an access transistor. Gate control transistors allow an erasing voltage to be applied to groups of memory cells or words comprising a small number of memory cells, for example from 8 to 16 memory cells. They thus have a very fine granularity in erasure. In addition, the access transistors insulate the floating gate transistors from bit lines and allow threshold voltages of different signs to be provided between erased memory cells and programmed memory cells. These memories are thus easy to implement but the memory cells occupy a significant surface due to their two-transistor structure.
FLASH-type memories only comprise one floating gate transistor by memory cell and thus have the advantage of being very compact in terms of surface of silicon occupied (number of memory cells per surface unit). On the other hand, the absence of access transistor requires positive threshold voltages for erased memory cells as well as for programmed memory cells, in order not to generate short circuits on the bit lines. Gate oxides must thus be thick to durably maintain the electric charges stuck in the floating gates, which causes a notable increase of the erasure time. More particularly, the erasure of FLASH memory cells is usually performed by tunnel effect while the writing thereof (programming) is performed by injecting hot electrons. The time required for writing memory cells is short, for example 5 microseconds, while the erasure time is long, for example 100 milliseconds. In addition, programming by injecting hot electrons causes the apparition of a high programming current, so that the number of memory cells which can be simultaneously written must be limited. Thus, writing memory cells is usually performed word by word, contrary to EEPROM memories which allow a whole page to be simultaneously written. Eventually, FLASH memories are only erasable by sector, a sector comprising transistors which low-potential terminals (source terminals for NMOS-type transistors) are linked to the same substrate.
FLASH memories have thus been originally dedicated to bulk storage. Various improvements were then suggested so that they could offer features coming closer to EEPROM memories, to open to FLASH memories application fields originally allotted to EEPROM memories. Globally, the aim of these improvements is to offer FLASH memories able to compete with EEPROM memories in terms of flexibility of use, without losing their advantages in terms of storage capacity per unit of silicon surface.
Among the improvements that have allowed the market of FLASH memories to evolve, the following can be quoted:                the design of a FLASH memory programmable by page, such as described by U.S. Pat. No. 6,839,285, assigned to STMicroelectronics S.A., which is the assignee of the present application. Such a memory comprises a volatile page buffer allowing it to receive data representing a whole page. An internal algorithm (executed by a wired-logic sequencer or a microprocessor) performs writing the page word by word but in a transparent way for the user, who is thus offered the ability to write a whole sector page by page instead of writing it word by word;        the design of a FLASH memory erasable by page, such as described by U.S. Pat. No. 6,807,103, assigned to STMicroelectronics S.A. In such a memory, inhibit voltages are applied to the memory cells which must not be erased within a sector being erased. An erase granularity is obtained which is not as fine as that of an EEPROM memory but which tends thereto (although some EEPROM memories are also erasable by page and not by word). Thanks to the inhibit voltages, the erasure step can be controlled in order to simultaneously erase one or more pages within a same sector, without affecting the other pages of the same sector;        the design of a FLASH memory programmable by word and erasable by page, or page-FLASH, such as described by U.S. Pat. No. 7,079,448, assigned to STMicroelectronics S.A. Such a memory also comprises a page buffer but the process of erasure by page according to U.S. Pat. No. 6,807,103 is combined with an internal algorithm simulating writing by word. The internal algorithm retrieves the words present in a target page and saves them in the page buffer with the new word(s) supplied by the user, to obtain an updated page. The target page is erased and the updated page is written therein, so that the target page then comprises the new word(s) and some words that were present in the initial page. The user may thus apply a command for writing a word without worrying about previously erasing the page, which is performed by the algorithm.        
This latest improvement has made it possible to commercialize FLASH memories with the same apparent functionalities as EEPROM memories, but in which some limitations remain, i.e.:                the long erasure time, which may be annoying for some applications. Indeed, the apparent time for writing a word is mainly imposed by the time for erasing the page, since the internal algorithm must erase the whole page each time a new word is written;        no protection against inopportune power interruptions. Indeed, if a power interruption occurs while erasing the target page and while the updated page is still in the volatile page buffer, all the data of the page are irreparably lost. Consequently FLASH memories cannot currently be used as embedded memories in integrated circuits intended for applications where the risk of power interruption is high. The applications typically are chip cards or electronic tags, in which the integrated circuits are powered by an external device (reader) and can disappear anytime in case of “tear off” (removing the card from the slot of the reader for a contact card, quickly taking the card away from the coil of the reader for an inductive coupling contactless card, etc.).        
It may thus be wished to improve FLASH-type memories and globally any type of non-volatile memory having all or part of the aforementioned features, according to at least one of the following improvement axes of:                enhancing the apparent time of data erasure;        enhancing the apparent time of data erasure without having to disrupt a flow of instructions;        protecting data against the risk of power interruption during the writing process.        
Each improvement axis is aimed at independently of the others or in combination with the others according to the applications concerned.
Regarding data protection against power interruptions, the patent application US2005/0251643 relates to a method of tearing proof programming (paragraph 0008) adapted to FLASH memories. The pages of the memory are used to memorize, in addition to useful data, a logic address of page and a count value. A look-up table allows a logic address and a physical address (electric address) to be associated. When a piece of data must be written in a page, the content of the page is copied out in a page buffer. The new piece of data is incorporated therein, while the count value is incremented. The updated content of the page is then written in another page, of the same logic address. The initial page is then erased. In summary, the pages are indexed in physical pages of any address and can be identified only from the logic address thereof. The fact of erasing the initial page after saving the updating in another physical page makes it possible to overcome the risk of losing data in the event of a power interruption during or after erasing the initial page. In case of doubt on the identity of the valid page at powering up, when two pages of same logic address are in the memory, the latest page is the one containing the highest count value.
This method requires managing a count value which must necessarily pass by zero, the size of the count field not being infinite, so that a new count value after reset may have a value inferior to a previous count value generated before reset. In addition, if a power interruption occurs while the initial page is being erased, the memory cells of the page are not completely erased. The data they comprise may have erroneous values, due to the fact that electric charges in the memory cells are undetermined as long as the erase process is not completed. Thus, after powering up after a power interruption, a count value read in incompletely erased memory cells may have an arbitrary value greater than the count value in the latest updated page. In these conditions, the old incompletely erased page comprising invalid data may be seen as the “good” page, while the true “good” page may be erased.
About the decrease in apparent erasure time, it appears that the writing method described in US2005/0251643 is based on an elementary step of writing new data without erasing previous data. It can be seen that this elementary step allows the apparent time for erasing a page to be reduced since writing updated page data is performed without previously erasing the initial page. However, it is not conceivable to permanently write data in erased pages, unless an infinite memory space is provided. The writing process may thus be interrupted, at a given time, to erase invalidated pages and to free memory space. Now, such an interruption may be not wished or not conceivable in some applications, in particular applications that require managing an uninterrupted flow of writing instructions.
Such an elementary step is also taught by the patent U.S. Pat. No. 6,212,105, but is implemented differently: when a new piece of data must be written, the new piece of data is temporarily written in an auxiliary location and the target location is erased; then the piece of data is written in the erased target location and the auxiliary location is erased. This method requires two consecutive erasure steps so that a piece of data is memorized in a target location, and is not adapted to memories with an erasure time greater than the writing time.